Device and method for compensating data run times

ABSTRACT

The invention relates to a device and a method for compensating data run times. The invention provides a plurality of series/parallel converters ( 2 ), a plurality of data word synchronisation units ( 3 ), a plurality of storage devices ( 4 ) and a plurality of parallel/series converters ( 5 ) for simultaneously reading out the data that is stored in the plurality of storage devices ( 4 ). Data run times are compensated, especially by inserting or rejecting at least one predetermined code word into/from the plurality of data streams.

[0001] The present invention relates to a device and a method forequalizing data delays in a multiplicity of serial input data streamsswitched, for example, by a switching network in a telecommunicationswitching system.

[0002] In particular, the invention relates to a device and a method forequalizing data delays used, for example, in Type D of the Siemens EWSDswitching system. This novel switching system is especiallycharacterized by a compressed data stream in which, for example, 16conventional line trunk groups are combined to form one data stream. Oneframe in a time-division multiplex system compressed in this mannerpreferably exhibits (in addition to 2×128 test channels) 16×128 payloadchannels with in each case 80 kbit/s. However, since different delayscan occur for the 16 combined line trunk groups, a data frame havingdifferent lengths is obtained in the compressed data stream which isessentially composed of the data streams of the 16 line trunk groups.More precisely, a fluctuation internal to the frame, which isessentially caused by delay differences of the line trunk groups, occursfor the associated data frames in the compressed data stream.

[0003] If, in addition, a multiplicity of such compression units combinein each case 16 line trunk groups, different start and end points arealso obtained again for the respective data frames between thecompressed data streams.

[0004] The invention is, therefore, based on the object of creating adevice and a method for equalizing data delays in a multiplicity ofserially compressed input data streams, wherein a multiplicity ofmutually synchronous data streams are output simultaneously and in phaseat the output.

[0005] According to the invention, this object is achieved by thefeatures of claim 1 with regard to the device and by the measures ofclaim 9 with regard to the method.

[0006] It is particularly by using a multiplicity of data wordsynchronization units for synchronizing the multiplicity of input datastreams at a data word level into a multiplicity of synchronizedparallel input data streams, the synchronizing at data word levelrepresenting an insertion or discarding of at least one predeterminedcode word into the multiplicity of input data streams, that a device anda method for equalizing data delays, in which the data streams outputcan be output absolutely synchronously and simultaneously without phaseshifts are obtained in a relatively simple manner.

[0007] A multiplicity of serial/parallel converters are preferably usedfor converting a compressed serial input data stream into a paralleldata stream of the multiplicity of input data streams which allows adata rate of the data stream to be significantly reduced. Before theserial/parallel conversion, the phases of the input data streams arealigned to the internal 184 MHz clock with the aid of so-called phasealigners. Phase aligners are analog circuits which are able to detect achange from 0 to 1 or conversely and can then allocate the signal to thepreferred phase.

[0008] The multiplicity of data word synchronization units preferably ineach case consist of variable serial storage units and an associatedcontrol unit, as a result of which the serial/parallel converted inputdata stream can be selectively processed further for different times.The buffers used are a multiplicity of storage devices which can besimultaneously read out via parallel/serial converters which results ina multiplicity of serial data streams at the output which are outputexactly synchronously and with identical data frame length.

[0009] Further advantageous embodiments of the invention arecharacterized in the further subclaims.

[0010] In the text which follows, the invention will be described ingreater detail by means of an exemplary embodiment and referring to thedrawing, in which:

[0011]FIG. 1 shows a simplified time representation of input and outputdata streams for illustrating an operation of the data delay equalizeraccording to the invention;

[0012]FIG. 2 shows a simplified representation of a data frame which ispreferably synchronized in the data delay equalizer according to theinvention;

[0013]FIG. 3 shows a simplified block diagram of the data delayequalizer according to the invention; and

[0014]FIG. 4 shows a simplified block diagram of a data wordsynchronization unit used in the data delay equalizer according to theinvention according to FIG. 3.

[0015]FIG. 1 shows a simplified representation of input and output datastreams for illustrating an operation of the data delay equalizer 1according to the invention, which is preferably used in a switchingnetwork of a telecommunication switching system.

[0016] As has already been indicated in the introduction to thedescription, the Type D of the Siemens EWSD switching system, forexample, has a multiplexer unit (not shown) or compression unit forcompressing a data stream supplied via line trunk groups and to beswitched. In this arrangement, 16 line trunk groups or their 128 payloadchannels, respectively, with 64 kbit/s in each case are preferablycompressed into a data stream of approx. 184 Mbit/s (which hasadditional test channels and test data). Since, however, respective datachannels in the data stream of the line trunk groups can be differentwith respect to time due to delay differences, data frames which deviatefrom one another are obtained for a multiplicity of compressed inputdata streams DIN0, DIN1 to DIN31.

[0017] According to FIG. 1, for example, an input data stream DIN0 has adata frame with a correct position in time and a length T. Bycomparison, however, an input data stream DIN1 can have a data framewhich, due to delay differences, has a shortened length T−Δt₁ and isadvanced by a time τ₁ compared with the correct data frame in the inputdata stream DIN0. In the same way, an input data stream DIN31 can have adata frame T+Δt₃₁ which is extended compared with the input data streamDIN0 and which, in addition, trails by a time of τ₃₁. The data delayequalizer according to the invention then equalizes the respective dataframes of the input data streams DIN0, DIN1 to DIN31 with differentlengths and starting times, in such a manner that they have synchronizeddata frames with a constant length and the same starting and end pointas output data streams DOUT0, DOUT1 to DOUT31. Such synchronized datastreams are absolutely necessary if, for example, in a down-streamswitching network of a telecommunication switching system, a temporaland/or spatial correlation of the data channels existing in the dataframes is to take place.

[0018]FIG. 2 shows a simplified representation of a frame structurewhich is obtained, for example, in the input data streams DIN0 to DIN31and output data streams DOUT0 to DOUT31. According to FIG. 2, datastreams of approx. 184 Mbit/s are synchronized and equalized, the datastreams consisting of test channels tstch, synw0 to synw3, asw0 to asw9(2 times 128 data channels) and payload channels payld (16 times 128data channels). FIG. 2 only shows a section of the complete framestructure (2304 data channels total) and, in particular, the relativechannel addresses 5 to 7, 9 to 15, 19 to 31, 33 to 63 and 69 to 126 arenot shown in order to simplify the frame structure. Only the furtherpayload channels payld are transmitted via these further relativechannel addresses of the synchronous time-division multiplex frame inthe switching network.

[0019] Accordingly, the time-division multiplex frame shown in FIG. 2 istransmitted with propagation delays shown in FIG. 1 or, respectively,deviations Δt₁ or Δt₃₁ internal to the frame and preferably consists of16×128 payload channels transmitted, for example, by 16 line trunkgroups and generated by multiplexer stages, not shown. The essentialfactor for the present invention is, however, the use of at least onepredetermined code word which is preferably located in the 2×128=256test channels. A synchronization data word synw0, which is located atthe first position in the data frame, is preferably used for thispredetermined code word. However, it is also possible to use the furthersynchronization data words synw1, synw2, synw3 or another data word ofthe data frame.

[0020] The reason why the synchronization data words synw0 to synw3 areneeded is firstly the detection of the frame start, beginning from whichthe remaining data words or data channels of a respective data frame canbe established. In the present invention, however, the predeterminedcode word synw0 is used for equalizing the aforementioned delaydifferences, for example, such an equalization essentially beingobtained by discarding or additionally inserting the predetermined codeword synw0 into the data stream. In this arrangement, a buffer orvariable serial storage unit generates the equalization of the delaydifferences by temporarily storing a variable volume of data (1 to 4data words). The insertion or discarding of the code word syncw0 is usedfor resetting the buffer into its operating state in specific situations(buffer too full or too empty).

[0021]FIG. 3 shows a simplified block diagram of the data delayequalizer according to the invention. According to FIG. 3, the datadelay equalizer according to the invention provides for thesynchronization of a multiplicity of input data streams DIN0 to DIN31 tomutually synchronized output data streams DOUT0 to DOUT31. According toFIG. 3, each input data stream DIN0 to DIN31 and the associated outputdata stream DOUT0 to DOUT31 in each case has a serial/parallel converter2, a data word synchronization unit 3, a storage device 4 and aparallel/serial converter 5. Accordingly, according to FIG. 3, a serialinput data stream DIN0 with approx. 184 Mbit/s is supplied to theserial/parallel converter 2 in which a bit-parallel input data stream isgenerated from the serial input data stream. The serial/parallelconverter preferably uses the width of one data word and in the presentexemplary embodiment, a 10-bit-wide parallel data stream hsdata isoutput to the data word synchronization unit 3. To accurately establisha position within a data frame, an address hsadr is also supplied to thedata word synchronization unit 3 via a parallel address bus. Thisresults in a considerable reduction of the data rate for the parallelinput data stream hsdata and hsadr as a result of which the technicalimplementation can be simplified, particularly for the data wordsynchronization unit.

[0022] The serial/parallel converters 2 also generate a data validitysignal hsdv which specifies whether valid data are present or not. Aclock signal clk92 is the 92 MHz system clock and a clock signal clk184represents a 184-MHz clock used by the serial/parallel converters andgenerated by clock doubling by means of a PLL.

[0023] The data word synchronization unit 3 synchronizes the parallelinput data streams at data word level, in dependence on these datastreams or data signals, into synchronized parallel input data streamsequdata and equadr which essentially correspond to the unsynchronizedinput data streams hsdata and hsadr. The synchronization is doneessentially by means of the centrally controlled output of data words. Acentral synchronization signal or master synchronization signal sync4with a fixed pattern of 5 clk92 clock pulses controls the output of thedata words. Inserting or removing the sync0 code word creates anequalization in the buffer to bring the latter close to its operatingstate.

[0024] The synchronized parallel input data streams equdata and equadrare then temporarily stored in a storage device 4 in such a manner thatthe parallel/serial converters 5, which read out simultaneously with themaster synchronization signal sync4 via read addresses rdadr, can outputread data rddata synchronously as output data streams DOUT0 to DOUT31. Awrite pointer, which is essentially controlled by the data wordsynchronization unit 3, is independent of a read pointer which iscontrolled by a unit (not shown) central to all 32 data streams.

[0025] Each storage device 4 preferably has 2304 storage cells with awidth of 10 bits in each case as a result of which a data volumetransmitted in one frame can be completely buffered.

[0026] The parallel/serial converters 5 are used for converting theparallel read data rddata into serial output data streams DOUT0 toDOUT31 of again approx. 184 Mbit/s. The output data streams DOUT0 toDOUT31 thus obtained are now completely synchronized to one another andin phase which is why they can be easily correlated in time and space bya downstream switching network.

[0027]FIG. 4 shows a simplified block diagram of the data wordsynchronization unit 3 used in the data delay equalizer 1 according tothe invention. According to FIG. 4, the data word synchronization unit 3essentially consists of a variable serial storage unit which representsthe buffer described above, and a control unit for controlling theserial storage unit. The variable serial storage unit essentiallyconsists of 4 serially connected selection registers 31 to 34 which ineach case have a register Q1, Q2, Q3 and Q4 and an associated selectionstage MUX1, MUX2, MUX3 and MUX4 for selecting different inputconnections. The selection stages MUX1 and MUX2 of the first twoselection registers 31 and 32 in each case have an input connection hfor retaining the data content or data word stored in the register, aninput connection i for inserting the predetermined code word synw0, aninput connection s for accepting a data content or data word of the nextregister and an input connection d for accepting actual input data orthe parallel input data streams hsdata and hsadr. In the presentexemplary embodiment, the selection register 34 only has the inputconnections h and d. The selection register 33 has the input connectionsh, s and d.

[0028] A state machine 35 essentially controls the selection stages MUX1to MUX4 of the selection registers 31 to 34 via control signals s1 to s4and in addition to the selection of the 4 input connections, a blankinstruction (don't care) can also be output and none of the inputconnections described above is activated. Furthermore, an address storedin the first register Q1 and last register Q4 can be detected viadetection units or comparator circuits 36 and 37 where preferably anaddress adr=0 is checked which specifies a position of the predeterminedcode word synw0 in the data frame. The detection units 36 and 37,together with the state machine 35, constitute the control unit forcontrolling the variable serial storage unit 31 to 34. The controlsignals are essentially a master synchronization signal sync4 which, ascommon synchronization signal, is also used by the parallel/serialconverters 5 for reading out the storage devices 4 and is essentiallyused as reference for writing into the storage device 4, and the signalhsdv which specifies that valid new data must be accepted.

[0029] The state machine 35 then controls a so-called fill f0 to f4 ofthe variable serial storage unit, which represents a FIFO memoryaccording to FIG. 4, in such a manner that, depending on the situation,a frame code word or the predetermined code word synw0 is inserted orremoved, or the data or the data stream are simply pushed through.Whereas a read address activated by the central unit continuously runsthrough or activates the 2304 addresses of the storage device 4, thewrite address is in each case supplied as equadr by the first selectionregister 31 and, in particular, can skip the address 0 or occupy ittwice which results in the read and write pointers approaching ordeparting. The storage device 4, which preferably consists of a RAM(random access memory) is preferably activated in a time-divisionmultiplex method and writing preferably occurs before reading. As aresult, there are no further problems if the read address and the writeaddress are the same.

[0030] If the data in the parallel input data stream hsdata and hsadrare too fast, i.e. a signal hsdv indicating this state occurs before themaster synchronization signal sync4, the buffer fills by one storagelocation or one selection register, respectively (Q3, Q2, Q1 containvalid data (only registers Q2 and Q1 contain valid data in normaloperation)). If, on the other hand, the input data are too slow, i.e.the master synchronization signal sync4 is already present and thesignal hsdv indicates that there are not yet any data, the bufferempties by one storage location (only Q1 still contains valid data). Inthis manner, the individual data frames are not corrupted and speeddifferences of up to 0.6 data words/frame can be equalized. It should bepointed out here that too fast or too slow an arrival of data must occur2304 times before the write pointer passes through the read point at thestorage device 4 (or conversely).

[0031] In the text which follows, the operation of the data wordsynchronization unit 3 is described in detail.

[0032] In principle, there are five fills f0 to f4 for the variableserial storage units 31 to 34 according to FIG. 3. A fill f0 indicatesthat there are no data in the registers as is the case, for example, inthe initial state. With a fill f1, only the register Q1 contains validdata. With a fill f2, registers Q1 and Q2 contain valid data and with afill f3, registers Q1 to Q3 and with a fill f4 the registers Q1 to Q4contain valid data. After switch-on or resetting of the data wordsynchronization unit 3, fill f0 initially exits. With the next clockpulse, the circuit is brought into fill f2 and the predetermined codeword synw0 is inserted into registers Q1 and Q2. t Q1 = xx Q2 = xx Q3 =xx Q4 = xx (f0) t + 1 Q1 = synw0 Q2 = synw0 Q3 = xx Q4 = xx (f2)

[0033] hsdv=0: s1=i, s2=i, s3=don't care, s4−don't care,

[0034] where t+1 means that one clock period of the 92-MHz clock signalhas started.

[0035] If, on the other hand, there are data for the variable serialstorage unit, i.e. hsdv=1, the state machine 35 sets the control signalsto s1=i, s2=d, s3=s4=don't care, which results in the following state: tQ1 = xx Q2 = xx Q3 = xx Q4 = xx (f0) t + 1 Q1 = synw0 Q2 = hsdata +hsadr Q3 = xx Q4 = xx (f2)

[0036] Fill f2 is the normal mode, where the data hsdata and hsadr areshifted through the selection registers 32 and 31.

[0037] In the text which follows, the behavior of the data wordsynchronization unit 3 for various situations deviating from normal modeare described. The data values xx are arbitrary data values produced bythe activation instruction “don't' care”. However, care has been takenthat such data are never output out of the register.

[0038] If data arrive too slowly, i.e. for example a new data item or anew data word only arrives after 11 clock pulses of the serial inputdata stream (184 MHz), the signal hsdv is at zero whereas the mastersynchronization signal sync4 is already at 1. In this case, the controlsignal s1=s is output and the other control signals s2 to s4 output the“don't care” instruction. t Q1 = data1 Q2 = data2 Q3 = xx Q4 = xx (f2)t + 1 Q1 = data2 Q2 = xx Q3 = xx Q4 = xx (f1)

[0039] If, on the other hand, the data arrive simultaneously, i.e. a newdata item arrives after exactly 10 clock pulses of the serial input datastream (184 MHz), the signal hsdv is at 1 and the master synchronizationsignal sync4 is also at 1. The state machine 35 activates the signals s1to s4 in such a manner that the following holds true:

s1=s, s2=d, s3 and s4=“don't care”. t Q1 = data1 Q2 = data2 Q3 = xx Q4 =xx (f2) t + 1 Q1 = data2 Q2 = hsdata + hsadr Q3 = xx Q4 = xx (f2)

[0040] In the case where there are no new data and no new mastersynchronization signal sync4, said state machine 35 activates thevariable serial storage unit in such a manner that the following holdstrue:

s1=h, s2=h, s3=s4=“don't care”. t Q1 = data1 Q2 = data2 Q3 = xx Q4 = xx(f2) t + 1 Q1 = data1 Q2 = data2 Q3 = xx Q4 = xx (f2)

[0041] If, on the other hand, the data are arriving too quickly, i.e. anew data item or data word arrives after only 9 clock pulses of theserial input data stream (184 MHz), the signal hsdv is at 1 and themaster synchronization signal sync4 is at 0. The state machine 35 thenactivates the variable serial storage unit as follows:

s1=h, s2=h, s3=d and s4=“don't care”. t Q1 = data1 Q2 = data2 Q3 = xx Q4= xx (f2) t + 1 Q1 = data1 Q2 = data2 Q3 = hsdata + hsadr Q4 = xx (f3)

[0042] The critical situations occur, in particular, if the data arearriving to quickly in fill f4 (i.e. after 9 clock pulses of the serialinput data stream (184 MHz)) or if the data are arriving too slowly infill f1 (i.e. after 11 clock pulses of the serial input data stream (184MHz)). With these fills, the address is observed by the detection units36 and 37 and in the case where the address matches the address of thepredetermined code word, a detection signal n1 and n4 is output.

[0043] Thus, for example, the data and the master synchronization signalsync4 can arrive at the same time, i.e. a new data item or a new datavalue arrives after 10 clock pulses of the serial input data stream (184MHz). The state machine 35 then receives the signals hsdv=1 and sync4=1and the detection signal n1=0. The variable serial storage unit is thenactivated as follows:

s1=d and s2=s3=s4=“don't care” t Q1 = data1 Q2 = xx Q3 = xx Q4 = xx (f1)t + 1 Q1 = hsdata + hsadr Q2 = xx Q3 = xx Q4 = xx (f1)

[0044] If, on the other hand, an address of the predetermined code wordis detected by the detection unit 37 in register Q1, i.e. n1=1, and ifthe signals hsdv=0 and sync4=1 are present, the activation by the statemachine 35 is as follows:

s1=h and s2=s3=s4=“don't care” t Q1 = synw0 Q2 = xx Q3 = xx Q4 = xx (f1)t + 1 Q1 = synw0 Q2 = xx Q3 = xx Q4 = xx (f1)

[0045] The case may also occur that the data arrive too slowly and themaster synchronization signal sync4 is already present. The signal hsdvis then at 0 and no address of the predetermined code word is detected,i.e. n1=0. In this case, the activation by the state machine 35 is asfollows:

s1=h and s2=s3=s4=“don't care” t Q1 = data1 Q2 = xx Q3 = xx Q4 = xx (f1)t + 1 Q1 = data1 Q2 = xx Q3 = xx Q4 = xx (f1)

[0046] In the storage device 4, writing occurs twice to the sameaddress. The write pointer is displaced with respect to the read point.

[0047] If, on the other hand, the data are arriving too quickly again,i.e. a new data item is arriving after only 9 clock pulses of the serialinput data stream (184 MHz), the signal hsdv is at 1 and the mastersynchronization signal sync4 is at 0. The following applies to the statemachine 35:

s1=h, s2=d, s3=s4=“don't care”. t Q1 = data1 Q2 = xx Q3 = xx Q4 = xx(f1) t + 1 Q1 = data1 Q2 = hsdata + hsadr Q3 = xx Q4 = xx (f2)

[0048] In the case where there are no new data and no mastersynchronization signal sync4, the state machine 35 should actually notcarry out any activation. If, however, the address of the data item inregister Q1 has the address of the predetermined code word, thepredetermined code word synw0 is inserted in register Q2 in order toreturn to normal operation or fill f2, respectively. This is theposition at which the synchronization word is inserted. The writepointer is thus displaced in the storage device 4. The signals hsdv andsync4 are then at 0 and the detection unit 37 outputs the signal n1=1.The following then applies for the state machine:

s1=h, s2=i, s3=s4=“don't care”. t Q1 = synw0 Q2 = xx Q3 = xx Q4 = xx(f1) t + 1 Q1 = synw0 Q2 = synw0 Q3 = xx Q4 = xx (f2)

[0049] The case may also occur that the data and the mastersynchronization signal sync4 arrive at the same time and the address ofthe data item in register Q4 matches the address of the predeterminedcode word. This situation is preferably used for creating free space inthe storage device 4. The write pointer in the storage device 4 jumpsforward by one address without corrupting data because address 0 isskipped which always contains the same data item, i.e. the predeterminedcode word. This jumping occurs only 4 pulses of the mastersynchronization signal sync4 later when the data have been shiftedthrough from the selection register 34 to the selection register 31. Thesignals hsdv, sync4 and n4 are then at 1 and the following applies forthe state machine 35:

s1=s, s2=s, s3=d, s4=“don't care”. t Q1 = data1 Q2 = data2 Q3 = data3 Q4= synw0 (f4) t + 1 Q1 = data2 Q2 = data3 Q3 = Q4 = xx (f3) hsdata +hsadr

[0050] If, on the other hand, the data are too fast again and theregister Q4 contains a different data item than the predetermined codeword synw0, the new data item is lost and the limit of the variableserial storage unit has been reached. This case results in the signalshsdv=1, sync4=0 and n4=0. The following holds true for the statemachine:

s1=h, s2=h, s3=h and s4=h. t Q1 = data1 Q2 = data2 Q3 = data3 Q4 = data4(f4) t + 1 Q1 = data1 Q2 = data2 Q3 = data3 Q4 = data4 (f4)

[0051] If, on the other hand, the data are too fast and the register Q4contains the predetermined code word synw0, the new data item isaccepted into register Q4 and the other data are kept in registers Q1 toQ3. This means that the predetermined code word synw0 is overwritten andthe write pointer skips the address 0 in the storage device 4. It isstill possible to prevent data corruption even in this case. The signalspresent at the state machine 35 are hsdv=1, sync4=0 and n4=1. Therefore,the following holds true for the state machine:

s1=s2=s3=h and s4=d. t Q1 = data1 Q2 = data2 Q3 = data3 Q4 = synw0 (f4)t + 1 Q1 = data1 Q2 = data2 Q3 = data3 Q4 = (f4) hsdata + hsadr

[0052] In consequence, it is possible to equalize speed differences of0.6 words/data frame.

[0053] In the above text, the invention has been described by means of adata frame having 2304 data channels and a data rate of 184 Mbit/s.However, it is not restricted to this and rather comprises all furtherdata frames having a number of channels and/or data rates deviatingtherefrom. In the same manner, the predetermined code word which isimplemented by the data word synw0 in the present invention can also bereplaced by one other or a number of other data words.

1. A device for equalizing data delays in a multiplicity of serial inputdata streams (DIN0 . . . DIN31), which input data streams (DIN0 . . .DIN31) exhibit at least one predetermined code word (synw0) in atime-division multiplex system, comprising a multiplicity ofserial/parallel converters (2) for converting the multiplicity of serialinput data streams (DIN0 . . . DIN31) into a multiplicity of parallelinput data streams (hsdata, hsadr); a multiplicity of data wordsynchronization units (3) for synchronizing the multiplicity of parallelinput data streams (hsdata, hsadr) at data word level (T) into amultiplicity of synchronized parallel input data streams (equdata,equadr), the synchronizing at data word level representing aninsertion/discarding of the at least one predetermined code word (synw0)into the multiplicity of parallel input data streams (hsdata, hsadr); amultiplicity of storage devices (4) for temporarily storing the parallelinput data streams (equdata, equadr) synchronized at data word level;and a multiplicity of parallel parallel/serial converters (5) for thesynchronous reading-out of the synchronized parallel input data streams(equdata, equadr) stored in the multiplicity of storage devices (4) andfor converting them into a multiplicity of serial output data streams(DOUT0 . . . DOUT31).
 2. The device as claimed in claim 1, characterizedin that the multiplicity of serial/parallel converters (2) also performa phase alignment of the multiplicity of input data streams (DIN0 . . .DIN31).
 3. The device as claimed in claim 1 or 2, characterized in thatthe multiplicity of data word synchronization units (3) in each caseexhibit a variable serial storage unit (31, 32, 33, 34) and a controlunit (35, 36, 37) for controlling the serial storage unit.
 4. The deviceas claimed in claim 3, characterized in that the variable serial storageunit exhibits a multiplicity of serially connected registers (Q1 . . .Q4) with associated selection stages (MUX1 . . . MUX4) for selectingdifferent input connections (h, d, i, s).
 5. The device as claimed inclaim 4, characterized in that the different input connections receiveas supplied data the data (h) contained in the associated register, theat least one predetermined code word (i), the data (s) contained in theupstream register or the parallel input data stream (d).
 6. The deviceas claimed in one of claims 3 to 5, characterized in that the controlunit exhibits a detection unit (36, 37) for detecting an address (adr0)of the at least one predetermined code word (synw0).
 7. The device asclaimed in one of claims 3 to 6, characterized in that the variablestorage unit (31 to 34) exhibits a variable FIFO memory.
 8. The deviceas claimed in one of claims 3 to 6, characterized in that the controlunit exhibits a state machine (35).
 9. A method for equalizing datadelays in a multiplicity of serial input data streams (DIN0 . . .DIN31), the input data streams exhibiting at least one predeterminedcode word (synw0) in a time-division multiplex system, consisting of thefollowing steps: a) converting the multiplicity of serial input datastreams (DIN0 . . . DIN31) into a multiplicity of parallel input datastreams (hsdata, hsadr); b) synchronizing the multiplicity of parallelinput data streams (hsdata, hsadr) at data word level (T) into amultiplicity of synchronized parallel input data streams (equdata,equadr), the synchronizing at data word level representing aninsertion/discarding of the at least one predetermined code word (synw0)in the multiplicity of parallel input data streams (hsdata, hsadr); c)storing the parallel input data streams (equdata, equadr) synchronizedat data word level in a multiplicity of storage devices (4); and d)synchronous reading out of the synchronized parallel input data steams(equdata, equadr) stored in the multiplicity of storage devices (4), andconverting them into a multiplicity of serial output data streams (DOUT0. . . DOUT31).
 10. The method as claimed in claim 9, characterized inthat in step a), a phase alignment of the multiplicity of input datastreams (DIN0 . . . DIN31) is also performed.
 11. The method as claimedin claim 9 or 10, characterized in that in step b), the data words ofthe parallel input data streams (hsdata, hsadr) are stored in unoccupiedserially connected registers (Q1 . . . Q4) if the data values arepresent before a master synchronization signal (SYNC4).
 12. The methodas claimed in claim 9 or 10, characterized in that in step b), the datavalues of the parallel input data streams (hsdata, hsadr) are shiftedfrom occupied serially connected registers if the data values arepresent after a master clock signal (SYNC4).
 13. The method as claimedin claim 9 or 10, characterized in that in step b), the predeterminedcode word (synw0) is discarded as data value if the data values arrivesynchronously with the master clock signal (sync4) and all seriallyconnected registers (Q1 to Q4) are occupied.
 14. The method as claimedin claim 9 or 10, characterized in that in step b), the predeterminedcode word (synw0) is inserted if it is stored as data word in one of theserially connected registers (Q1 to Q4) and the registers do not havenormal occupancy (f2).